1. Field of the Invention
The present disclosure relates to the field of integrated circuit manufacturing, and, more particularly, to the field of depositing materials with a two-step or a multi-step deposition process.
2. Description of the Related Art
During the process of manufacturing sophisticated semiconductor devices, such as modern CPUs, a plurality of different material layers are deposited on each other and patterned to define required device features. In general, subsequent material layers should exhibit a good adhesion to each other while at the same time maintain the integrity of each individual layer, i.e., chemical reaction of adjacent layers and/or diffusion of atoms from one layer into the other layer should be avoided. To meet these requirements, an intermediate layer is often required to provide good adhesion and to suppress diffusion and thus undue interference between neighboring materials during processing and operation. A typical example for such requirements in the fabrication of semiconductor devices is the formation of interconnect plugs and metal interconnects, wherein openings and trenches having a bottom region and a sidewall region have to be provided with a corresponding intermediate layer, that is, a conductive barrier layer, so that a subsequently deposited conductive material exhibits good adhesion to the surrounding dielectric layer and undue interaction during processing and operation may be avoided. In advanced semiconductor devices, the interconnect plugs may be formed of tungsten-based metal that is provided in a dielectric material which is typically comprised of silicon dioxide including a bottom etch stop layer typically formed of silicon nitride.
Other examples of the formation of contact plugs relates to copper-based techniques. For example, in modern integrated circuits, copper is often used as conductive material for forming electrical connections between the circuit elements. To this end, one or more wiring levels or layers are provided, which include metal lines and metal regions, establishing the electrical connections. While aluminum is a well-approved metal in the semiconductor industry, in modern integrated circuits, highly conductive metals such as copper and alloys thereof are increasingly used to accommodate the high current densities encountered during the operation of the devices, as the ongoing reduction of feature sizes also leads to reduced dimensions of the metal lines and vias. Consequently, the metallization layers may comprise metal lines and vias formed from copper and copper alloys. To provide the required adhesion and diffusion blocking characteristics to the copper, a conductive barrier layer is usually provided. Typical materials for the barrier layer are tantalum, tantalum nitride, titanium, titanium nitride and the like. The copper metallization layer may be formed on the basis of well-established single or dual damascene or inlay techniques, in which a dielectric layer may be deposited first and may be subsequently patterned so as to receive via openings or trenches which may then, commonly or separately, be filled with the copper-based material. The trenches and vias are subsequently coated with an appropriate barrier material, wherein subsequently copper may be filled in by electroplating or any other appropriate deposition techniques. In other damascene regimes, a via layer may be formed first and subsequently the interlayer dielectric material may be deposited hi an appropriate thickness so as to form therein trenches for receiving the respective metal lines. Thereafter, the barrier layer may be formed on the basis of well-established techniques, for example sputter techniques or chemical vapor deposition (CVD) techniques. On the barrier layer, a copper seed layer may be provided, for example by sputtering. Filling in the copper-based metal may then be performed either by sputter deposition techniques or by plating techniques, for example, electroplating or electroless plating. After filling in the copper-based metal for forming the metal lines, any excess material, such as excess copper and excess barrier material, may be removed by chemical mechanical polishing (CMP), electrochemical polishing and the like.
In general, the electrical resistance of the barrier layer metal is significantly higher than the resistance of the tungsten-based material forming in the contact plug so that the thickness of the barrier metal layer is selected to be as small as possible in order to avoid an undue increase of the overall resistance of the contact plug.
In modern integrated circuits, openings (so-called vias) are formed exhibiting an aspect ratio that may be as high as approximately 8:1 or more, and the opening may have a diameter of 0.1 μm or smaller. The aspect ratio of such openings is generally defined as the ratio of the depth of the opening to the width of the opening. Accordingly, it is extremely difficult to form a thin uniform barrier metal layer on the entire sidewalls, especially at the bottom corners, to effectively avoid direct contact of the metal with the surrounding dielectric material. In other words, it is difficult to form a barrier metal layer that adequately covers all surfaces of the openings while on the other hand being as thin as possible.
An example of a contact plug as described above is an interconnect plug for providing connection to a circuit element, such as a transistor that is formed above an appropriate semiconductor substrate. The circuit element may be comprised of one or more contact regions, such as a gate electrode and drain and source regions. The circuit clement is covered by a dielectric material, which may comprise a contact etch stop layer which may be formed of silicon nitride, and an interlayer dielectric material, which is typically silicon dioxide. Contact openings are formed in the dielectric material to connect the respective contact regions of the circuit element. A conductive barrier layer, e.g., a titanium liner and a titanium nitride layer in a tungsten contact technology, is fanned within the contact openings. The titanium liner and the titanium nitride layer may be formed to enhance the reliability of the subsequent deposition of a tungsten-based material.
As already mentioned before, the liners and barrier layers described above may be formed on the basis of an ionized physical vapor deposition, such as sputter deposition. The term “sputtering” or “sputter deposition” describes a mechanism in which atoms are ejected from a surface of a target material upon being hit by sufficiently energetic particles. Sputtering has become a dominant technique for deposition of titanium, titanium nitride and the like. Although, in principle, improved step coverage could be obtained by using CVD techniques, sputter deposition is widely used for the deposition of a liner for the following reasons.
Sputter deposition allows the relatively uniform deposition of layers over large-area substrates since sputtering may be accomplished from large-area targets. Control of film thickness by sputter deposition is relatively simple as compared to CVD deposition and may he achieved by selecting a constant set of operating conditions, wherein the deposition time is then adjusted to achieve the required film thickness. Moreover, the composition of compounds such as titanium nitride may be controlled more easily and precisely in sputter deposition processes compared to CVD. Additionally, the surfaces of the substrates to be processed may he sputter-cleaned prior to the actual film deposition so that any contamination of the surface may be efficiently removed and further recontamination prior to the actual deposition process may be effectively suppressed. For an efficient deposition for moderately thin material within the contact openings having a moderately high aspect ratio, so-called ionized sputter deposition techniques are used in which target atoms liberated from the target are efficiently ionized by a respective plasma ambient while removing towards the substrate. On the basis of a DC or RF bias, the directionality of the moving ionized target atoms may be significantly enhanced, thereby enabling the deposition of target material at the bottom of the contact openings, even for high aspect ratios.
Depending on the respective process parameters, the layer thickness at the bottom of the contact hole may be significantly thicker compared to a thickness at the sidewalls of the contact openings. In particular, at lower sidewall portions, the corresponding material thickness may be significantly thinner compared to the thickness at the bottom of the contact opening. However, a reliable and thus minimum layer thickness may be required, especially at the bottom sidewall portions, in order to substantially prevent any adverse interaction of the subsequently deposited tungsten and the dielectric layer.
As described above, deposition of materials in high aspect ratio contact holes may be performed by chemical vapor deposition processes or by physical vapor deposition processes. However, as indicated above, configurations exist where it is desirable to use physical vapor deposition although chemical vapor deposition processes are more likely to uniformly cover the surface of high aspect ratio holes. A primary method for depositing films by physical vapor deposition is sputtering. One problem associated with obtaining good bottom step coverage utilizing physical vapor deposition is a material overhang at the shoulder, i.e., at the corner of sidewalk and the top surface of contact openings.
FIG. 1A schematically show an example of a contact hole 10 in a dielectric layer 12, the contact hole having sidewalls 13 and a bottom 14. FIG. 1B shows the contact hole 10 of FIG. 1A in a further advanced manufacturing stage, where a material layer 16 has been deposited on the dielectric layer 12 and in the contact hole 10. At upper corners 18, a material overhang 20 is formed. Such a material overhang 20 hinders appropriate filling of the contact hole 10 and also hinders material 16 to be deposited on sidewalls 13 of the contact hole 10. Another problem is obtaining adequate bottom step coverage. In particular, the layer thickness of the material layer 16 on sidewalls 13 close to the bottom 14 of the contact hole 10 is decreased with respect to the thickness of the material layer on the dielectric layer 12, as indicated in FIG. 1B. To overcome this problem, it has been proposed to use a two-step sputter process, wherein, during a first step, a desired material is deposited in the contact hole. During this deposition process, a shoulder may form on the upper edge of the contact hole as shown in FIG. 1B. Subsequently, in a re-sputtering step, the shoulder may be removed or at least reduced. Re-sputtering may be performed by applying a bias voltage to the substrate and/or by varying the working gas, e.g., in terms of pressure and/or composition. The time period for this re-sputtering step may be in the range of less than 60 seconds. The re-sputtering further leads to a redistribution of the re-sputtered atoms, part of which are deposited lower in the contact hole, thereby improving step coverage. Upon appropriate choice of process parameters, a relatively uniform film thickness of the material layer 16 along the sidewalls 13 of the contact hole 10 may be achieved by performing a re-sputter step, as indicated in FIG. 1C. Further, a beveled upper edge 22 of the material layer 16 at the corner 18 is usually obtained which is advantageous in the subsequent filling of the remaining hole 24.
Generally, metal sputter deposition processes are characterized by a decrease in the deposition rate as the sputter target life degrades. The decrease and inconsistencies in the deposition rate are driven by various reasons. Material may build up on chamber shields, e.g., a collimator. Further, target erosion may influence sputter uniformity over the target. Further, the power supplied to the target may vary and hence may result in variations of the sputter rate. Further, variations in gas flow and pressure may also give rise to variations in the deposition rate. For two-step and/or multi-step metal sputtering deposition processes, a decrease in the position rate may be difficult to compensate. A common method of open-loop compensation, which is typically employed internally to the sputter tool itself, is limited to simple one-step processes.
The present disclosure is directed to various methods and systems that may avoid or at least reduce, the effects of one or more of the problems identified above.